Dynamic schottky barrier MOSFET device and method of manufacture

ABSTRACT

A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of and priority to U.S. provisionalpatent application No. 60/513,410, filed Oct. 22, 2003. This applicationalso claims the benefit of and priority to U.S. provisional patentapplication No. 60/514,041, filed Oct. 24, 2003. Each of the aboveprovisional patent applications is incorporated by reference herein intheir entirety.

FIELD OF THE INVENTION

The present invention relates to devices for regulating the flow ofelectric current, and has specific application to the fabrication ofthese devices in the context of an integrated circuit (“IC”). Moreparticularly, it relates to a transistor for regulating the flow ofelectric current having metal source and/or drains formingSchottky-barrier or Schottky-like contacts to a channel region.

BACKGROUND OF THE INVENTION

One type of transistor known in the art is a Schottky-barrier metaloxide semiconductor field effect transistor (Schottky-barrier MOSFET orSB-MOS). As shown in FIG. 1, the SB-MOS device 100 comprises asemiconductor substrate 110 in which a source electrode 120 and a drainelectrode 125 electrode are formed, separated by a channel region 140having channel dopants. The channel region 140 is the current-carryingregion of the substrate 110. For purposes of the present invention, thechannel region 140 in the semiconductor substrate extends verticallybelow the gate insulator 150 to a boundary approximately aligned withthe bottom edge of the source 120 and bottom edge of the drain 125electrodes. The channel dopant concentration profile typically has amaximum concentration 115, which is below the source 120 and drain 125electrodes, and thus outside of the channel region 140. For the purposeof the present invention, channel dopants are not constrained to beprovided exclusively within the channel region 140, but may be found inregions substantially outside of the channel region 140.

For a SB-MOS device at least one of the source 120 or the drain 125contacts is composed partially or fully of a metal silicide. Because atleast one of the source 120 or the drain 125 contacts is composed inpart of a metal, they form Schottky or Schottky-like contacts 130,135with the substrate 110 and the channel region 140. A Schottky contact isdefined as a contact formed by the intimate contact between a metal anda semiconductor, and a Schottky-like contact is defined as a contactformed by the close proximity of a semiconductor and a metal. TheSchottky contacts or Schottky-like contacts or junctions 130, 135 may beprovided by forming the source 120 or the drain 125 from a metalsilicide. The channel length is defined as the distance from the source120 contact to the drain 125 contact, laterally across the channelregion 140.

The Schottky or Schottky-like contacts 130, 135 are located in an areaadjacent to the channel region 140 formed between the source 120 anddrain 125. An insulating layer 150 is located on top of the channelregion 140. The insulating layer 150 is composed of a material such assilicon dioxide. The channel region 140 extends vertically from theinsulating layer 150 to the bottom of the source 120 and drain 125electrodes. A gate electrode 160 is positioned on top of the insulatinglayer 150, and a thin insulating layer 170 surrounds the gate electrode160. The thin insulating layer 170 is also known as the spacer. The gateelectrode 160 may be doped poly silicon. The source 120 and drain 125electrodes may extend laterally below the spacer 170 and gate electrode160. A field oxide 190 electrically isolates devices from one another.An exemplary Schottky-barrier device is disclosed in Spinnaker's U.S.Pat. No. 6,303,479.

Another type of MOSFET transistor known in the art is a conventionalimpurity-doped source-drain transistor or conventional MOSFET. Thisdevice is similar to the SB-MOS device shown in FIG. 1. The keydifference is that the metal source-drain regions 120,125 of the SB-MOSare replaced with impurity doping in the semiconductor substrate for theconventional MOSFET.

One of the important performance characteristics for a MOSFET device isthe drive current (I_(d)), which is the electrical current from sourceto drain when the applied source voltage (V_(s)) is grounded, and thegate (V_(g)) and drain (V_(d)) are biased at the supply voltage(V_(dd)). Drive current is one of the important parameters thatdetermines circuit performance. For example, the switching speed of atransistor scales as I_(d), so that higher drive current devices switchfaster, thereby providing higher performance integrated circuits.

FIG. 2 shows the relationship of drive current (I_(d)) 232 for varyinggate voltage (V_(g)) and drain voltage (V_(d)) 231 for a SB-MOS and aconventional MOSFET. One characteristic of SB-MOS device I_(d)-V_(d)curves is the sub-linear shape for low V_(d) 231, as shown by the solidlines 210,215,220,225,230. Each of the I_(d)-V_(d) curves210,215,220,225,230 has a different V_(g). The I_(d)-V_(d) profile atlow V_(d) is known as the turn-on characteristic. Conventional MOSFETtransistor technologies have a linear I_(d)-V_(d) turn-on characteristicat low V_(d), as shown by the dashed lines 235,240,245,250,255 in FIG.2. Each of the I_(d)-V_(d) curves 235,240,245,250,255 has a differentV_(g). The sub-linear I_(d)-V_(d) turn-on characteristic of the SB-MOSdevice increases as the channel length decreases and can potentiallyreduce transistor performance, possibly reducing the effective switchingspeed of the device for example. Sub-linear turn-on has been observed inthe literature and referenced as a reason why SB-MOS devices will not beof practicable use in integrated circuits (B. Winstead et al., IEEETransactions on Electron Devices, 2000, pp. 1241-1246). Industryliterature consistently teaches that the Schottky barrier height φ_(b)should be reduced or made less than zero in order to minimize thesub-linear turn-on phenomenon and thus to make SB-MOS device performancecompetitive with alternative MOSFET device technologies (J. Kedzierskiet al., IEDM, 2000, pp. 57-60; E. Dubois et al., Solid StateElectronics, 2002, pp. 997-1004; J. Guo et al., IEEE Transaction onElectron Devices, 2002, pp. 1897-1902; K. Ikeda et al., IEEE ElectronicDevice Letters, 2002, pp. 670-672; M. Tao et al., Applied PhysicsLetters, 2003, pp. 2593-2595).

There is a need in the industry for teaching a SB-MOS device and methodof fabrication that provides a means for improving the turn-oncharacteristic thereby providing improved performance.

BRIEF SUMMARY OF THE INVENTION

In one aspect, the present invention provides a method of fabricating aSchottky barrier MOSFET (SB-MOS) device wherein at least one of thesource and drain contact regions is comprised of a metal and wherein theSB-MOS device includes an interfacial layer located between at least oneof the metal source or drain electrodes and the semiconductor substrate,thereby forming a Schottky or Schottky-like contact. In one embodimentof the present invention, the interfacial layer is comprised of aconducting, semiconducting, or insulating material.

While multiple embodiments are disclosed, still other embodiments of thepresent invention will become apparent to those skilled in the art fromthe following detailed description, which shows and describesillustrative embodiments of the invention. As will be realized, theinvention is capable of modifications in various obvious aspects, allwithout departing from the spirit and scope of the present invention.Accordingly, the drawings and detailed description are to be regarded asillustrative in nature and not restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a sectional view of a prior art Schottky-barriermetal oxide semiconductor field effect transistor (“MOSFET”);

FIG. 2 illustrates transistor curves for a SB-MOS device and an impuritydoped source-drain MOSFET device;

FIG. 3 illustrate a sectional view of an exemplary embodiment of thepresent invention metal-insulator-semiconductor (MIS) source-drainSB-MOS device;

FIG. 4 illustrates an exemplary embodiment of the present inventionprocess using implantation of the semiconductor substrate;

FIG. 5 illustrates an exemplary embodiment of the present inventionprocess using a patterned silicon film on a thin gate insulator;

FIG. 6 illustrates an exemplary embodiment of the present inventionprocess using a formation of thin insulator sidewalls, and exposure ofthe silicon in the gate, source and drain areas;

FIG. 7 illustrates an exemplary embodiment of the present inventionprocess using an at least partially isotropic etch;

FIG. 8 illustrates an exemplary embodiment of the present inventionprocess using a formation of a thin interfacial layer;

FIG. 9 illustrates an exemplary embodiment of the present inventionprocess using an anisotropic etch;

FIG. 10 illustrates an exemplary embodiment of the present inventionprocess using a metal deposition, silicidation anneal, and removal ofunreacted metal;

FIG. 11 illustrates band diagrams for an exemplary zero electric fieldtwo-terminal MIS diode device;

FIG. 12 illustrates band diagrams for an exemplary biased two-terminalMIS diode device;

FIG. 13 illustrates band diagrams for different gate bias conditions forthe source-channel junction for a SB-MOS device having only metal in thesource-drain regions and no interfacial insulator layer; and

FIG. 14 illustrates band diagrams for different gate bias conditions forthe source-channel junction for an exemplary embodiment of the presentinvention MIS source-drain SB-MOS device.

FIG. 15 illustrates an alternative exemplary embodiment of the presentinvention process using a metal gate.

FIG. 16 illustrates a cross-sectional view of another exemplaryembodiment of the present invention process using a metal-insulatorsemiconductor (MIS) source-drain SB-MOS device.

FIG. 17 illustrates a cross-sectional view of yet another exemplaryembodiment of the present invention process using ametal-insulator-semiconductor (MIS) source-drain SB-MOS device.

DETAILED DESCRIPTION

In general, the present invention provides method of fabrication ofSB-MOS devices. In one embodiment of the present invention, the methodincludes providing a semiconductor substrate and doping thesemiconductor substrate and channel region. The method further includesproviding a first electrically insulating layer in contact with thesemiconductor substrate. The method further includes providing a gateelectrode on the first insulating layer, providing a second insulatinglayer around the gate electrode including the gate electrode sidewalls,and exposing the substrate on one or more areas proximal to the gateelectrode. In the present invention, the term proximal is defined asbeing located within a lateral distance away of approximately 500 Å fromone or more said objects. For example, in the previous sentence, thesubstrate is exposed in one or more areas proximal to the gateelectrode, or the one or more areas are located within a lateraldistance away of approximately 500 Å from the gate electrode. The methodfurther includes etching of the exposed areas proximal to the gateelectrode using a partially isotropic etch. The method further includesproviding an interfacial layer on the exposed semiconductor substrate atleast in areas proximal to the gate electrode and first insulatinglayer, the interfacial layer comprising a conducting, semiconducting, orinsulating material, but preferably an insulating material. The methodfurther includes using an anisotropic etch to expose the semiconductorsubstrate in areas proximal but not below the gate electrode andproviding an insulating layer on the gate electrode sidewalls. Themethod further includes depositing a thin film of metal and reacting themetal with the exposed substrate, such that a metal silicide forms onthe substrate. The method further includes removing any unreacted metal.

One of the advantages of the present invention is that the metal sourceand drain electrodes provide significantly reduced parasitic seriesresistance (˜10 Ω-μm) and contact resistance (less than 10⁻⁸ Ω-cm²). Thebuilt-in Schottky barrier at the Schottky contacts provides superiorcontrol of off-state leakage current. The device substantiallyeliminates parasitic bipolar action, making it unconditionally immune tolatch-up, snapback effects, and multi-cell soft errors in memory andlogic. Elimination of bipolar action also significantly reduces theoccurrence of other deleterious effects related to parasitic bipolaraction such as single event upsets and single cell soft errors. Thedevice of the present invention is easily manufacturable, requiring twofewer masks for source/drain formation, no shallow extension or deepsource/drain implants, and a low temperature source/drain formationprocess. Due to low temperature processing, integration of new,potentially key materials such as high K gate insulators, strainedsilicon and metal gates is made easier

FIG. 3 shows a cross-sectional view of a preferred exemplary embodimentof the present invention, as exemplified by ametal-insulator-semiconductor (MIS) source-drain SB-MOS structure 300.This embodiment comprises a SB-MOS device in which at least one of thesource 305 or drain 310 regions consist of metal, so that there is nodoping in the source and/or drain regions. In this embodiment, thedevice includes an interfacial layer 315, comprised of a conducting,semiconducting, or insulating material, placed between at least one ofthe metal source 305 or drain 310 electrodes and the semiconductorsubstrate 301, the interfacial layer 315 being in contact with a channelregion 320, thereby forming a first Schottky barrier or Schottky-likecontact 325 to the channel region 320. In one preferred embodiment, theinterfacial layer 315 is an insulating material. A second Schottky orSchottky-like barrier 330 is formed along the portion of the metalsource 305 and/or drain 310 electrodes having direct contact between themetal and the semiconductor substrate 301. The present invention doesnot recognize any limitations in regards to what types of metals may beused in affecting the teachings of the present invention. Thus, metalscommonly used at the transistor level, such as titanium, cobalt and thelike, are specifically anticipated, as well as a plethora of more exoticmetals and other alloys. Various metal silicides may also be employed,such as Platinum silicide, Palladium silicide, Iridium Silicide, and/orthe rare-earth silicide, all of which should be considered as beingwithin the scope of the teachings of the present invention. It is alsonoted that in another embodiment, the metal source/drain regions 305,310may be composed of multiple layers of metals and/or metal silicides.

In one preferred embodiment, an Indium or Arsenic layer 340 is used asthe channel and substrate dopants for a Schottky barrier N-type MOSFET(SB-NMOS) or a Schottky barrier P-type MOSFET (SB-PMOS) devices,respectively. These dopant atoms are used due to their relatively lowrates of diffusion through the silicon lattice (compared to Phosphorousand Boron, the other two possible candidates for channel and substratedopants). This allows for greater thermal budget during fabrication ofthe device, and therefore less statistical variation in thecharacteristics of the finished product. The present invention does notrecognize any limitations in regards to what types of dopants may beused in the present invention.

In one preferred embodiment, the gate electrode 345 is fabricated fromBoron or Phosphorous doped polysilicon films for the P-type and N-typedevices, respectively. In this instance, Boron or Phosphorous are useddue to their large solid-solubilities (compared to Arsenic and Indium).Alternatively, a metal gate may be used. In the present embodiment, thegate electrode 345 may be less than 100 nm in width (corresponding tothe channel length L). The gate electrode 345 has an electricallyinsulating sidewall 350, which may be an oxide, a nitride, or amulti-layer stack of differing insulating materials.

Devices are separated from each other by an insulating layer (notshown), such as a thermally grown oxide (called a Field Oxide) thatworks in conjunction with channel and substrate dopants to electricallyisolate the devices from each other. This field oxide may be providedfor by a conventional process, such as a LOCOS or STI process.

One exemplary process for the fabrication of a MIS source/drain SB-MOSdevice is illustrated in FIGS. 4-10. While this process is exemplary ofthe broad teachings of the present invention, it will be instructive toone skilled in the art to teach the fundamental concepts of the presentinvention. It is noted that this exemplary process is not limitive andthat additional processes which are specifically anticipated by thepresent invention will be apparent to one skilled in the art. Thisexemplary process flow may be described as follows:

FIG. 4 shows a silicon substrate 410 that has means for electricallyisolating transistors from one another. Throughout the discussionherein, there will be examples provided that make reference to asemiconductor substrate on which an SB-MOS device is formed. The presentinvention does not restrict the semiconductor substrate to anyparticular type. One skilled in the art will readily realize that manysemiconductor substrates may be used for SB-MOS including silicon,silicon germanium, gallium arsenide, indium phosphide, strainedsemiconductor substrates, silicon on insulator, substrates of variouscrystallographic orientation such as <110> and <100>. In anotherembodiment, the silicon substrate 410 is strained. The use of a strainedsilicon substrate 410 in combination with a SB-MOS device results inadditional improvements in power and speed performance. In anotherembodiment, the substrate is SOI. An SOI substrate comprises asemiconductor material, such as silicon having a thickness ofapproximately 20 nm to 100 nm, on a buried insulating material, such assilicon dioxide (SiO₂) having a thickness of approximately 100 nm to 400nm, which is formed on a semiconductor substrate. These substratematerials and others may be used and are within the scope of theteachings of the present invention.

As shown in FIG. 4, a thin screen oxide 420 is grown on the substrate410 to act as an implant mask. In one embodiment, the oxide is grown toa thickness of about 200 Å. The appropriate channel dopant species 430is then ion-implanted through the screen oxide 420 such that a maximumdopant concentration 440 is provided to a pre-determined depth D1 (450)in the silicon. In one embodiment the channel dopant species is Arsenicfor P-type devices and Indium for N-type devices, however any otherchannel dopant species commonly used at the transistor for P-type orN-type devices is specifically anticipated by the present invention. Inanother embodiment, the channel dopant concentration profile variessignificantly in the vertical direction but is generally constant in thelateral direction. In a further embodiment, the depth D1 450 of themaximum dopant concentration is approximately 20 to 200 nm.

As shown in FIG. 5, the screen oxide is then removed in a chemical etch,and a thin gate insulator 510, such as silicon dioxide is grown. In oneembodiment the screen oxide etch is comprised of hydrofluoric acid,however other chemistries commonly used to etch oxide, including bothwet and dry etches, are specifically anticipated. In another embodiment,the thin gate insulator is comprised of silicon dioxide with a thicknessof approximately 6 to 50 Å. In a further embodiment, a material having ahigh dielectric constant (high K) is provided. Examples of high Kmaterials are those materials having dielectric constants greater thanthat of silicon dioxide, including for example nitrided silicon dioxide,silicon nitride, and metal oxides such as TiO₂, Al₂O3, La₂O₃, HfO₂,ZrO₂, CeO₂, Ta₂O₅,WO₃, Y₂O₃, and LaAlO₃, and the like. The gateinsulator growth is immediately followed by providing an in-situ dopedsilicon film. The gate insulator growth is immediately followed byproviding an in-situ doped silicon film. The film is heavily doped with,for example, Phosphorous for an N-type device and Boron for a P-typedevice. Using lithographic techniques and a silicon etch that is highlyselective to the gate insulator, the gate electrode 520 is patterned asshown in the process step 500 illustrated in FIG. 5. In anotherexemplary embodiment, a metal gate electrode may be provided. In anotherembodiment, following gate electrode patterning, additional channeldopants are provided and result in a channel dopant concentrationprofile that varies significantly in both the vertical and lateraldirections.

As shown in FIG. 6, a thin insulator is then provided on the top surface625 and sidewalls 610 of the silicon gate electrode 520. In oneembodiment, the thin insulator is a thermally grown oxide that has athickness of approximately 50 to 500 Å. In another embodiment, thethermally grown thin oxide is provided by a rapid thermal oxidation(RTO) process having a maximum temperature of 900 to 1200° C. for adwell time of 0.0 to 60 seconds. One skilled in the art will readilyrealize that there are many manufacturing methods for providing thininsulator layers such as deposition. One skilled in the art will furtherrealize that other materials may be used for the thin insulator such asnitrides and the insulating layer may be comprised of multiple insulatormaterials. An anisotropic etch is then used to remove the insulatorlayer on the horizontal surfaces (and thus expose the silicon 620, 625)thereby exposing the horizontal surface, while preserving the insulatorlayer on the vertical surfaces. In this way, a sidewall insulator 610 isformed. It will be obvious to one skilled in the art that the gateelectrode 520 and the sidewall insulator 610 function as a mask to theanisotropic etch such that the openings in the thin insulator layer onthe silicon substrate are proximal with the gate electrode 520. In theembodiment in which the thin insulator is approximately 50 to 500 Å, theopenings in the thin insulator layer will be proximal to the gateelectrode 520 and located within a lateral distance away from the gateelectrode 520 that is approximately 50 to 500 Å. In one exemplaryembodiment, the silicon surface 620 is recessed below the bottom of thegate insulator to a depth D2 630 of approximately 1 nm to approximately5 nm. In the embodiment in which an RTO process is used to provide thesidewall insulator, the dopants both in the gate electrode and in thechannel region of the device are electrically activated simultaneouslywith the sidewall insulator formation, as shown in the process step 600illustrated in FIG. 6.

As shown in FIG. 7, a second etch process step etches the semiconductorsubstrate both laterally and vertically. This etch is known as apartially isotropic etch. In one embodiment, a partially isotropic etchhaving a lateral etch rate at least 10% of a vertical etch rate is used.In another embodiment, a partially isotropic etch having a vertical etchrate at least 10% of a lateral etch rate is used. The depth of thesecond etch is D3 710. The lateral etch displaces the exposed verticalsidewall of the semiconductor substrate 720 laterally a distance L1 730from the edge of the sidewall oxide 610 to a position below the gateelectrode 520. Because the etch is partially isotropic, L1 may be lessthan or equal to ten times D3 or D3 may be less than or equal to tentimes L1. In yet another embodiment, an etch having a lateral etch rateapproximately equal to a vertical etch rate is used. For thisembodiment, D3 may be approximately equal to L1. The lateral etchprovides a means for decreasing the channel length by an amount ofapproximately two times L1. In one embodiment, the vertical etch rate issufficient to form an exposed vertical surface 720 of the semiconductorsubstrate 410 laterally below the gate electrode 520, as shown in theprocess step 700 illustrated in FIG. 7. In yet a further embodiment, thepartially isotropic etch is provided by any one or a combination of aSF₆ dry etch, a HF:HNO₃ wet etch, or any wet or dry etch that iscommonly used for the purpose of etching semiconductor material.

As shown in FIG. 8, an interfacial layer 810 is formed on the exposedhorizontal and vertical surfaces of the semiconductor substrate 410. Inone embodiment, the interfacial layer 810 is a thermally grown siliconnitride (Si₃N₄) having a thickness of less than about 2 nm as shown inthe process step 800 illustrated in FIG. 8. In another embodiment, theinterfacial layer 810 is comprised of either a metal, semiconductor orinsulating material.

Process step 900 shown in FIG. 9, provides a third anisotropic etch toetch through the interfacial layer 810 and expose the semiconductorsubstrate 410, at least in areas proximal but not below the gateelectrode 520 and gate electrode sidewall spacer 610. This etch exposesthe silicon substrate to a depth D4 (910).

As shown in FIG. 10, the next step encompasses depositing an appropriatemetal as a blanket film on all exposed surfaces. Deposition may beprovided by either a sputter or evaporation process or more generallyany thin film formation process. In one embodiment, the substrate isheated during metal deposition to encourage diffusion of the impingingmetal atoms to the exposed silicon surface 810, below the gateinsulator. In one embodiment, this metal is approximately 250 Å thickbut more generally approximately 50 to 1000 Å thick. Throughout thediscussion herein there will be examples provided that make reference toSchottky and Schottky-like barriers and contacts in regards to ICfabrication. The present invention does not recognize any limitations inregards to what types of Schottky interfaces may be used in affectingthe teachings of the present invention. Thus, the present inventionspecifically anticipates these types of contacts to be created with anyform of conductive material or alloy. For example, for the P-typedevice, the metal source and drain 1010,1020 may be formed from any oneor a combination of Platinum Silicide, Palladium Silicide, or IridiumSilicide. For the N-type device, the metal source and drain 1010,1020may be formed from a material from the group comprising Rare EarthSilicides such as Erbium Silicide, Dysprosium Silicide or YtterbiumSilicide, or combinations thereof. Any other metals commonly used at thetransistor level, such as titanium, cobalt and the like, arespecifically anticipated, as well as a plethora of more exotic metalsand other alloys. In another embodiment, the silicided source/drain canbe made of multiple layers of metal silicide, in which case otherexemplary silicides, such as titanium silicide or tungsten silicide forexample, may be used.

The wafer is then annealed for a specified time at a specifiedtemperature so that, at all places where the metal is in direct contactwith the silicon, a chemical reaction takes place that converts themetal to a metal silicide 1010, 1020, 1030. In one embodiment, forexample, the wafer is annealed at about 400° C. for about 45 minutes ormore generally approximately 300 to 700° C. for approximately 1 to 120min. The metal that was in direct contact with a non-silicon surfacesuch as the gate sidewall spacer 610 is left unreacted and therebyunaffected.

A wet chemical etch is then used to remove the unreacted metal whileleaving the metal-silicide untouched. In one embodiment, aqua regia isused to remove Platinum and HNO₃ is used to remove Erbium. Any otheretch chemistries commonly used for the purpose of etching Platinum orErbium, or any other metal systems used to form Schottky orSchottky-like contacts are specifically anticipated by the presentinvention. The MIS source-drain SB-MOS device is now complete and readyfor electrical contacting to gate 520, source 1010, and drain 1020, asshown in the process step 1000 illustrated in FIG. 10.

As a result of this exemplary process, Schottky or Schottky-likecontacts are formed to the channel region 1040 and substrate 410respectively wherein the Schottky contacts are located at a positioncontrolled by the partially isotropic etch process. In one embodiment,the interface 810 of the source 1010 and drain 1020 electrodes to thechannel region 1040 is located laterally below the spacer 610 and isaligned with the edge of the sides of the gate electrodes 1040. Inanother embodiment, the interface 810 of the source 1010 and drain 1020electrodes to the channel region 1040 is located laterally below thespacer 610 and partially below the gate electrode 520. In yet anotherembodiment, a gap is formed between the interface 810 of the source 1010and drain 1020 electrodes to the channel region 1040 and the edge of thesides of the gate electrode 520.

While traditional Schottky contacts are abrupt, in the present inventionan interfacial layer is utilized between the silicon substrate and themetal. This interfacial layer may be ultra-thin, having a thickness ofapproximately 10 nm or less. Thus, the present invention specificallyanticipates Schottky-like contacts and their equivalents to be useful inimplementing the present invention. Furthermore, the interfacial layermay comprise materials that have conductive, semi-conductive, orinsulator-like properties. For example, ultra-thin interfacial layers ofoxide or nitride insulators may be used, or ultra-thin dopant layersformed by dopant segregation techniques may be used, or ultra-thininterfacial layers of a semiconductor such as Germanium may be used toform Schottky-like contacts, among others.

By using the techniques of the present invention, several benefitsoccur. First, the metal-insulator-semiconductor (MIS) structure providesa means for dynamically controlling the effective Schottky barrierheight of the SB-MOS device. Referencing FIG. 11, band diagrams for anexemplary MIS diode device are shown. Basic operating principles andterminology are described in the PhD thesis of Mark Sobolewski, StanfordUniversity, 1989.

In FIG. 11, the band diagram for an N-type MIS diode is shown in anidealized zero electric field state. In practice, a finite built-infield may be present in the interfacial insulator layer. The metal workfunction φ_(m) (1105) and semiconductor electron affinity χ_(s) (1110)are referenced to the conduction band (1115) of the insulating layer.E_(fm) (1120) and E_(fs) (1125) are the metal and semiconductor Fermilevels respectively, while E_(c) (1130) is the conduction band. V_(d)(1135) and V_(i) (1140) are the potential drops in the semiconductorsubstrate depletion region and insulator respectively, while ζ (1145) isthe separation between the Fermi level and the conduction band deep inthe bulk of the semiconductor. The insulator thickness is t_(i) (1150)and the effective Schottky barrier height φ_(b,1) (1155) is defined tobe the separation between E_(fm) (1120) and E_(c) (1130) at thesilicon-insulator interface. In the idealized zero electric field state,φ_(b,1) (1155) is determined by φ_(m) (1105) and χ_(s) (1110), bothphysical properties of the system.φ_(b1)=φ_(m)−χ_(s).  Equation 1

In FIG. 12, a positive bias is applied to the metal relative to thegrounded semiconductor substrate, thereby shifting E_(fm) (1120) up by−V (1205) relative to E_(fs) (1125). This induces an electric field atthe interfacial insulator layer ε_(s) (1210), thereby creating apotential drop V_(i) (1215) across the insulator. In this state, the neweffective Schottky barrier height φ_(b,2) (1220) is given by Equation 2.φ_(b,2)=−χ_(s) −V _(i)=φ_(b,1) −V _(i)  Equation 2

Therefore, the potential drop V_(i) (1215) in the insulator interfaciallayer provides a means for dynamically changing the effective Schottkybarrier height φ_(b,2) (1220) between the metal and the semiconductorsubstrate by an amount V_(i) (1215). The potential drop in the insulatorlayer will be a function of the insulator layer thickness t_(i) (1150),the metal bias 1205 and therefore the electric field strength ε_(s) 1210at the insulator, and the insulator dielectric constant.

These principles can be applied to a SB-MOS device having MIS source anddrain contacts. When considering the MOSFET operational characteristics,the segment of the MIS source electrode in contact with the channelregion and immediately below the gate insulator dominates the deviceperformance, particularly in the on-state. Furthermore, due to the threeterminal MOSFET structure, the electrostatic fields in the channelregion of the MOSFET have a two-dimensional character. For this reason,the induced Schottky barrier modulation along the interface of thesource electrode to the channel region varies, having a maximum wherethe source intersects the channel and gate insulator. The followingdiscussion references an “active” source MIS region. This is the sourceMIS structure immediately below the gate insulator, which extendsapproximately 5-20 nm below the gate insulator along the source-channeljunction. It is the region where the gate induced electric fieldprovides the strongest potential drop in the MIS insulator and whereapproximately over 90% of current emission from the source electrodeoccurs in the on-state.

In the off-state, with the gate and source contacts grounded and thedrain biased at V_(dd), a first electric field will be provided at theinsulator of the source MIS structure, causing a first potential dropacross the insulator V_(i,d) and therefore a first effective Schottkybarrier height φ_(bd). However, an important difference between a threeterminal MIS source-drain MOSFET device of the present invention and atwo terminal MIS diode is the third terminal, the gate electrode, whichis located in close proximity to the MIS structure at the source.Depending on the MOSFET geometry, the gate electrode may be displacedfrom the source by approximately 1 nm while the drain electrode isdisplaced by 10's of nm. In the on-state, the source contact remainsgrounded while the drain and gate are both biased at V_(dd). Due to theclose proximity of the gate to the source, a second electric field,substantially larger than the first electric field, is formed in theactive source MIS region, thereby inducing a second potential dropacross the insulator V_(idg) and a second effective barrier heightφ_(bdg). Along the vertically oriented portion of the source electrode,adjacent to the channel region, the gate-induced electric fielddecreases while moving down from the gate insulator, thereby causingV_(idg) to decrease and therefore φ_(bdg) to increase as a function ofposition. The Schottky barrier height modulation dramatically affectsthe current emission characteristics from the source electrode.

For SB-MOS technology, current emission from the source electrode isprovided by a tunneling mechanism in the on-state. FIG. 13 shows theband diagrams for three different gate biases (V_(g)) at thesource-channel interface for a conventional n-type SB-MOS device nothaving an MIS structure. As shown, in the region near the sourceelectrode, the conduction band forms a nearly triangular barrier 1310,1320, 1330. The total tunneling current through this Schottky barrier isexponentially sensitive to the barrier height φ_(b) 1340 but also theelectric field at the Schottky barrier contact ε_(s) 1350,1351,1352. Itis important to note that for this device, the barrier height φ_(b) 1340is fixed, and the gate modulates ε_(s), 1350, 1351, 1352 therebyincreasing the tunneling current as the gate bias is increased.

FIG. 14 shows the band diagrams for three different gate biases Vg atthe source-channel interface for an N-type SB-MOS device having an MISsource/drain structure. Only a portion of the bands of the MIS insulatorlayer are shown. In the region near the source electrode, the conductionband again forms a nearly triangular barrier 1410, 1420, 1430. For a MISdevice, the effective barrier height b 1440, 1441, 1442 is modulated bythe gate at the same time ε_(s) 1450, 1451, 1452 is modulated, therebyproviding two mechanisms for increasing the tunneling current, not justone (ε_(s) modulation) as is the case for a conventional SB-MOS device.This effect will occur for any V_(d) as long as V_(g) is biased and willthereby provide improved drive current for low V_(d), reducing thesub-linear turn-on characteristic at low V_(d) and improving the turn-onperformance of the SB-MOS device and providing higher drive current.

It is important that the insulator not be too thick, as the chargecarrier tunneling probability will eventually be inhibited by theinsulator barrier, thereby diminishing the net benefit of modulating theSchottky barrier to a lower level.

An additional benefit of the MIS source-drain SB-MOS device structure isthat for a sufficiently thick insulator interfacial layer, it will blockthe penetration of the metal states, which cause pinning in the silicon.(see for example D. Connelly, et. al. in “A New Route to Zero-BarrierMetal Source-Drain MOSFETs” presented at the 2003 VLSI Symposium, Kyoto,2003). This provides a means for affecting the initial barrier heightprior to any gate biasing, and may allow for the introduction of othermetals or metal alloys to be used as metal source-drain contacts.

In summary, an interfacial layer disposed between the metal source-draincontacts and the semiconductor substrate of an MIS source/drain SB-MOSdevice provides a means for affecting the unbiased initial effectiveSchottky barrier height, and furthermore provides a means fordynamically adjusting the Schottky barrier height by changing the gate,and secondarily the drain bias. This enables the introduction ofnumerous metals, metal silicides and/or metal alloys for affecting thepreferred embodiments of the teachings of the present invention, whichotherwise would not be possible if employing a pure metal-semiconductorSchottky barrier junction having no interfacial layer. It furtherenables substantially improved low V_(d) turn-on characteristics andhigher drive currents.

FIG. 15 shows a cross-sectional view of another preferred exemplaryembodiment of the present invention, as exemplified by ametal-insulator-semiconductor (MIS) source-drain SB-MOS structure 1500.This embodiment comprises a SB-MOS device in which at least one of thesource 1505 or drain 1510 regions consist of a first 1506 and second1507 metal, so that there is no doping in the source and/or drainregions. In this embodiment, the device includes an interfacial layer1515, either conducting, semiconducting, or insulating, placed betweenthe first metal 1506 and the semiconductor substrate 1501, theinterfacial layer 1515 being in contact with a channel region 1520,thereby forming a first Schottky barrier or Schottky-like contact 1525to the channel region 1520. The interfacial layer 1515 is furthermoreplaced between the second metal 1507 and the semiconductor substrate,thereby forming a second Schottky barrier or Schottky-like contact 1526to the semiconductor substrate 1501.

The first and second metals may be provided using the followingexemplary process. Following process step 800 shown in FIG. 8, a firstmetal is isotropically deposited, including in any regions below thegate electrode. The first metal is subsequently anisotropically etched.A second metal is then directionally deposited, to minimize depositionon sidewalls of the gate electrode and a short isotropic etch is used toremove any metals deposited on the gate electrode sidewalls or othervertical surfaces. The transistor is masked and a more thoroughisotropic etch of the second metal is provided. In one exemplaryembodiment, the first metal, located primarily below the gate electrode,is selected for its Schottky barrier height properties to the channelregion in order to optimize the drive and/or to optimize the leakagecurrent of the device. In another exemplary embodiment, the secondmetal, which fills the bulk of the source-drain regions may be chosenbased on its conductivity, with high conductivity metals preferred.Furthermore, it may be engineered as an alloy or a stack of metals sothat for example it presents a mid-gap barrier between the bulk of thesource/drain regions and the semiconductor substrate in order to controloff-state leakage for both SB-NMOS and SB-PMOS simultaneously. An alloyor metal stack may also be employed for the second metal for optimizingconductivity or for its process integration properties, such as itsability to provide an etch stop when forming contact holes for themetallization and wiring of the transistor device. The aforementionedselection criteria for the first and second metals applies to this andall other embodiments disclosed previously or subsequently.

The present invention does not recognize any limitations in regards towhat types of first or second metals may be used in affecting theteachings of the present invention. Thus, metals commonly used at thetransistor level, such as titanium, cobalt and the like, arespecifically anticipated, as well as a plethora of more exotic metalsand other alloys that provide an appropriate first and second Schottkybarrier to optimize device performance. Various metal silicides may alsobe employed such as Platinum silicide, Palladium silicide, IridiumSilicide, and/or the rare-earth silicides, all of which should beconsidered as being within the scope of the teachings of the presentinvention. In another embodiment, the first and second metals are thesame and may be provided in the same process step or in two differentprocess steps.

An Indium or Arsenic layer 1540 is used as the channel and substratedopants for an NMOS or PMOS devices, respectively. Boron may also beused as a channel and substrate dopant for the NMOS device. The gateelectrode 1545 is fabricated from Boron or Phosphorous doped polysiliconfilms for the P-type and N-type devices, respectively. Alternatively, ametal gate may be used. The gate electrode 1545 has a gate insulator1550 and an electrically insulating sidewall 1551, which may be anoxide, a nitride, or a multi-layer stack of differing insulatingmaterials as shown in device 1500 in FIG. 15.

FIG. 16 shows a cross-sectional view of yet another preferred exemplaryembodiment of the present invention, as exemplified by ametal-insulator-semiconductor (MIS) source-drain SB-MOS structure 1600.This embodiment comprises a SB-MOS device in which at least one of thesource 1605 or drain 1610 regions consist of a first 1606 and second1607 metal, so that there is no doping in the source and/or drainregions. In this embodiment, the device includes a first interfaciallayer 1615, either conducting, semiconducting, or insulating, placedbetween the first metal 1606 and the semiconductor substrate 1601, thefirst interfacial layer 1615 being in contact with a channel region1620, thereby forming a first Schottky barrier or ‘Schottky-like’contact 1625 to the channel region 1620. A second thick interfaciallayer 1617 is furthermore placed between the second metal 1607 and thesemiconductor substrate 1601. The second interfacial layer 1617 may beprovided by angled, rotated deposition. The second interfacial layer1617 is not necessarily composed of the same material or materials ofthe first interfacial layer 1615. The second interfacial layer providesa large potential barrier to current transport from the second metal tothe semiconductor substrate, thereby reducing source-drain leakagecurrent. In another exemplary embodiment, the first and second metalsare the same and may be provided in the same process step or in twodifferent process steps.

The second interfacial layer may be provided by a source-drain localizedLOCOS process, otherwise called a micro-LOCOS process. Following processstep 700 shown in FIG. 7, a thin pad oxide is deposited, followed bydeposition of a thicker nitride layer. An anisotropic etch is used toetch through the nitride and pad oxide in the source-drain region,exposing the semiconductor substrate. A thick oxide is thermally grownon the exposed semiconductor substrate and a phosphoric strip removesany exposed nitride layers. A short hydrofluoric acid dip removes thepad oxide on the vertical sidewalls of the channel region, followed byformation of a thin thermally grown nitride layer. An advantage of thispresent embodiment is it avoids placing a thick insulator on top of thegate electrode, which may be a result of a straight deposited insulator.A first metal is isotropically deposited, including in any regions belowthe gate electrode and is anisotropically etched. A second metal isdirectionally deposited, to minimize deposition on sidewalls of the gateelectrode and a short isotropic etch is used to remove any metalsdeposited on the gate electrode sidewalls or other vertical surfaces.The transistor is masked and a more thorough isotropic etch of thesecond metal is provided. The present invention does not recognize anylimitations in regards to what types of first or second metals may beused in affecting the teachings of the present invention. Thus, metalscommonly used at the transistor level, such as titanium, cobalt and thelike, are specifically anticipated, as well as a plethora of more exoticmetals and other alloys that provide an appropriate first Schottkybarrier to optimize device performance. Various metal silicides may alsobe employed, such as Platinum silicide, Palladium silicide, IridiumSilicide, and/or the rare-earth silicides, all of which should beconsidered as being within the scope of the teachings of the presentinvention.

An Indium or Arsenic layer 1640 is used as the channel and substratedopants for an NMOS or PMOS devices, respectively. Boron may also beused for the channel and substrate dopant for NMOS. The gate electrode1645 is fabricated from Boron or Phosphorous doped polysilicon films forthe P-type and N-type devices, respectively. Alternatively, a metal gatemay be used. The gate electrode 1645 has a gate insulator 1650 and anelectrically insulating sidewall 1660, which may be an oxide, a nitride,or a multi-layer stack of differing insulating materials as shown indevice 1600 in FIG. 16.

Referencing FIG. 16, in yet another exemplary embodiment, ametal-semiconductor (MIS) source-drain SB-MOS structure may be employed.In this structure, the first interfacial layer 1615 would not beprovided, so that the first metal 1606 is in direct contact with thechannel region 1620. To emphasize, no interfacial layer is providedbetween the first metal 1606 and the channel region 1620. In thisembodiment, the first metal layer 1606 may be a metal, an alloy or asilicide. Furthermore, the second metal layer 1607 may be provided usingthe same methods described above, including for example directionaldeposition techniques.

FIG. 17 shows a cross-sectional view of yet another preferred exemplaryembodiment of the present invention, as exemplified by ametal-insulator-semiconductor (MIS) source-drain SB-MOS structure 1700.This embodiment comprises a SB-MOS device in which the source 1705and/or drain 1710 regions consist of a first 1706 and optionally asecond 1707 metal, so that there is no doping in the source and/or drainregions. In this embodiment, the device includes an interfacial layer1715, either conducting, semiconducting, or insulating, placed betweenthe first metal 1706 and the semiconductor substrate 1701, theinterfacial layer 1715 being in contact with a channel region 1720,thereby forming a first Schottky barrier or ‘Schottky-like’ contact 1725to the channel region 1720. The source 1705 and drain 1710 regions arein contact with a buried oxide 1717, such as that of an SOI substrate.The buried oxide 1717 provides a large potential barrier to currenttransport from the second metal 1707 to the semiconductor substrate1701, thereby reducing source-drain leakage current. In anotherexemplary embodiment, the first and second metals 1706,1707 are the sameand may be provided in the same process step or in two different processsteps.

The first and second metals 1706,1707 may be provided using thefollowing exemplary process. Following process step 800 shown in FIG. 8,the first metal 1706 is isotropically deposited, including in anyregions below the gate electrode 1745. The first metal 1706 issubsequently anisotropically etched. The second metal 1707 is thendirectionally deposited, to minimize deposition on sidewalls 1760 of thegate electrode 1745 and a short isotropic etch is used to remove anymetals deposited on the gate electrode sidewalls 1760 or other verticalsurfaces. The transistor is masked and a more thorough isotropic etch ofthe second metal 1707 is provided. The first and second metals 1706,1707are selected based on criteria previously noted. In another embodiment,the first and second metals 1706,1707 are the same and may be providedin the same process step or in two different process steps.

An Indium or Arsenic layer is used as the channel dopants for an NMOS orPMOS devices, respectively. Boron may also be used for the channel andsubstrate dopant for NMOS. The gate electrode 1745 is fabricated fromBoron or Phosphorous doped polysilicon films for the P-type and N-typedevices, respectively. Alternatively, a metal gate may be used. The gateelectrode 1745 has a gate insulator 1750 and the electrically insulatingsidewall 1760, which may be an oxide, a nitride, or a multi-layer stackof differing insulating materials as shown in the structure 1700 in FIG.17.

Referencing FIG. 17, in yet another exemplary embodiment, ametal-semiconductor (MIS) source-drain SB-MOS structure may be employed.In this structure, the interfacial layer 1715 would not be provided, sothat the first metal 1706 is in direct contact with the channel region1720. To emphasize, no interfacial layer is provided between the firstmetal 1706 and the channel region 1720. In this embodiment, the firstmetal layer 1706 may be a metal, an alloy or a silicide. Furthermore,the second metal layer 1707 may be provided using the same methodsdescribed above, including for example directional depositiontechniques.

The present invention is particularly suitable for use in situationswhere short channel length MOSFETs are to be fabricated, especially inthe range of channel lengths less than 100 nm. However, nothing in theteachings of the present invention limits application of the teachingsof the present invention to these short channel length devices.Advantageous use of the teachings of the present invention may be hadwith channel lengths of any dimension. The present invention furtheranticipates the use of a plethora of channel, substrate and well implantprofiles. For example, the channel implant may be a simple profile whoseprofile varies significantly in the vertical direction and is generallyconstant in the lateral direction. Or, for example the channel implantprofile may be approximately symmetric, having a lateral maximumconcentration in approximately the center of the channel region. Or,laterally and vertically non-uniform doping profiles may be used.

Although the present invention has been described with reference topreferred embodiments, persons skilled in the art will recognize thatchanges may be made in form and detail without departing from the spiritand scope of the invention. The present invention may be used with anyof a number of channel, substrate and well implant profiles. The presentinvention applies to any use of metal source drain technology, whetherit employs SOI substrate, strained Silicon substrate, SiGe substrate,FinFET technology, high K gate insulators, and metal gates. This list isnot limitive. Any device for regulating the flow of electric currentthat employs metal source-drain contacts will have the benefits taughtherein.

While, the present invention is particularly suitable for use withSB-MOS semiconductor devices, it may also be applied to othersemiconductor devices. Thus, while this specification describes afabrication process for use with SB-MOS devices, this term should beinterpreted broadly to include any device for regulating the flow ofelectrical current having a conducting channel that has two or morepoints of electrical contact wherein at least one of the electricalcontacts is a Schottky or Schottky-like contact.

1. A MOSFET device comprising: a gate electrode on a semiconductorsubstrate; a source electrode and a drain electrode on the semiconductorsubstrate, wherein at least one of the source electrode and the drainelectrode is metal; and an interfacial layer between the substrate andat least one of the metal source and drain electrodes.
 2. The device ofclaim 1 wherein the interfacial layer is disposed in areas at leastproximal to the gate electrode.
 3. The device of claim 1 wherein anentire Schottky or Schottky-like junction between the substrate and atleast one of the metal source and drain electrodes incorporates theinterfacial layer.
 4. The device of claim 1 wherein at least in areasproximal to the gate electrode, a Schottky or Schottky-like junctionbetween the substrate and at least one of the metal source and drainelectrodes incorporates the interfacial layer.
 5. The device of claim 1wherein at least one of the metal source and drain electrodes having theinterfacial layer form a Schottky or Schottky-like junction to thesubstrate.
 6. The device of claim 1 wherein the interfacial layercomprises an insulator.
 7. A method of manufacturing a MOSFET device forregulating a flow of electrical current, the method comprising:providing a gate electrode on a semiconductor substrate; exposing thesemiconductor substrate in an area proximal to the gate electrode;etching the semiconductor substrate on the exposed area using an atleast partially isotropic etch; depositing a thin film of metal in theetched area of the semiconductor substrate; and reacting the metal withthe semiconductor substrate such that at least one of a Schottky orSchottky-like source electrode and drain electrode is formed.
 8. Themethod of claim 7 wherein the etching step is performed using an etchhaving a lateral etch rate of from approximately one-tenth to ten timesof a vertical etch rate.
 9. The method of claim 7 wherein the etchingstep is performed using an etch having approximately the same lateraland vertical etch rates.
 10. The method of claim 7 wherein the gateelectrode is provided by the steps comprising: providing a thininsulating layer on the semiconductor substrate; depositing a thinconducting film on the thin insulating layer; patterning and etching thethin conducting film to form the gate electrode; and forming at leastone thin insulating layer on at least one sidewall of the gateelectrode.
 11. The method of claim 7 further comprising removingunreacted metal from the MOSFET device after forming the Schottky orSchottky-like source and drain electrodes.
 12. The method of claim 7wherein the reacting step is performed by thermal annealing.
 13. Themethod of claim 7 wherein the source electrode and the drain electrodeare formed from a member of the group consisting of: Platinum Silicide,Palladium Silicide and Iridium Silicide, and channel dopants in thesemiconductor substrate are selected from the group consisting of:Arsenic, Phosphorous, and Antimony.
 14. The method of claim 7 whereinthe source electrode and the drain electrode are formed from a member ofthe group consisting of the rare-earth suicides, and channel dopants inthe semiconductor substrate are selected from the group consisting of:Boron, Indium, and Gallium.
 15. The method of claim 7 wherein Schottkyor Schottky-like contact is formed at least in areas adjacent to achannel between the source and drain electrodes.
 16. The method of claim7 wherein an entire surface of the at least one of the source electrodeand the drain electrode forms a Schottky or Schottky-like contact withthe semiconductor substrate.
 17. The method of claim 7 wherein beforethe step of providing the gate electrode, dopants are introduced intothe semiconductor substrate.
 18. The method of claim 7 wherein thesemiconductor substrate has a channel dopant concentration that variessignificantly in a vertical direction and is generally constant in alateral direction.
 19. A method of manufacturing a device for regulatinga flow of electrical current, the method comprising: exposing asemiconductor substrate in an area proximal to a gate electrode; etchingthe semiconductor substrate on the exposed area using an at leastpartially isotropic etch; and depositing and thermally annealing a thinfilm of metal with the semiconductor substrate such that a Schottky orSchottky-like source electrode and drain electrode is formed.
 20. Themethod of claim 19 wherein the etching step is performed using an etchhaving a lateral etch rate of from approximately one-tenth to ten timesof a vertical etch rate.
 21. The method of claim 19 wherein the etchingstep is performed using an etch having approximately the same lateraland vertical etch rates.
 22. The method of claim 19 wherein the etchingstep is performed using an etch having lateral and vertical etch ratessuch that a channel width of the device is reduced by betweenapproximately 1 and 50 percent.
 23. The method of claim 19 wherein thesemiconductor substrate is heated during the depositing step, toencourage surface diffusion of metal atoms along a surface of thesemiconductor substrate.